As the demand has increased for semiconductor chips that offer more functions per chip and shorter times for performing those functions, semiconductor device dimensions have been pushed deeper and deeper into the sub-micron regime. Smaller devices readily translate into more available area for packing more functional circuitry onto a single chip. Smaller devices are also inherently advantageous in terms of shorter switching times, as will now be discussed. Using CMOS FET technology as a typical example, smaller device dimensions have resulted in shorter switching times for a number of reasons. In order for a device to switch a given node on a chip from one logic level to another, the effective load capacitance, C.sub.1, presented to that device must be charged or discharged through some effective resistance, R.sub.e, comprised of device channel resistance and device interconnect resistance. Consequently, from basic circuit theory, it follows that switching times will tend to decrease as the values of both R.sub.e and C.sub.l are reduced. Historically, increasingly smaller device dimensions have helped to reduce R.sub.e, by means of shorter device channel lengths as well as the increased freedom for using shorter interconnect lines between devices. Shorter interconnect lines and their lower. associated, cross sectional area have also helped to reduce C.sub.l. More over, further reductions in C.sub.l have also resulted from the smaller PN junction capacitance and parasitic device capacitance values that are inherently available from smaller devices. Accordingly, as a result of continued reductions in device geometry, from one device generation to the next, great strides have been made in the speed performance of today's chips. However, as device dimensions have progressed deeper and deeper into the sub micron regime, the technological and manufacturing challenges for continuing such scaling efforts at acceptable rates have sharply increased. This has, in turn, prompted a number of innovative techniques for squeezing additional speed out of each succeeding generation of CMOS technology. Since the 1970's the resolution limits of optical lithography have been reduced from about 1.5 microns down to about 0.2 microns and lower. Advancements, such as shorter exposure wavelengths, variable numerical aperture exposure lenses and phase shift masks, have contributed immensely to the progress that has occurred. Likewise, anti-reflective coatings have also increasingly been incorporated into semiconductor process sequences, as a means of further enhancing critical dimension (CD) control during sub-micron photolithography steps. In addition, other techniques have been developed for pushing device speeds beyond what would, otherwise, be obtained by simply scaling device sizes down to the latest CD limits of each succeeding generation of optical lithography.
U.S. Pat. No. 5.434,093 to Chau. et. al., teaches a method for using an inverted spacer structure as a means of fabricating FET devices with channel lengths that are shorter than the minimum critical dimension, CD, that can be obtained from a given photolithography image. The gate region of the device is first photolithographically defined as a trench in an oxide layer. A second overlying layer of conformal oxide is then deposited and subsequently anistropically etched back, whereby the thicker portion of the conformal layer along the side walls of the aforementioned trench is allowed to remain as an inverted spacer structure. The inverted spacer structure effectively extends the side walls of the aforementioned trench inward to a new reduced size that is considerably less than that of the original trench. The reduced trench is then used to define a polysilicon gate that is considerably smaller than the original trench. The polysilicon gate is formed by first depositing an overlying layer of polysilicon and then using a Chemical Mechanical Polishing, CMP, step to remove the polysilicon from the top surface of the oxide surrounding the aforementioned trench. The end result is an FET gate with an associated channel length that is smaller than the minimum critical dimension, CD, of the photolithography technology that was employed.
U.S. Pat. No. 5,773,348 to Wu, teaches a method, somewhat similar to that of Chau, et. al., for forming FET devices with gate lengths that are below the minimum critical dimension, CD, that any given generation of photolithography equipment. An inverted spacer structure is used, along with additional features such as a punch through stopping ion implant layer and an amorphous silicon layer, for the FET gate electrode, which is then converted to polysilicon by subsequent high temperature annealing.
U.S. Pat. No. 5,786,256 to Gardner, et. al., also teaches a method, somewhat similar to that of Chau, et. al., for forming FEF devices with gate lengths that are below the minimum critical dimension, CD, that is resolvable by any given generation of photolithography equipment. An inverted spacer structure is also used to form the gate electrode. In addition, a second set of spacers is used as part of the process sequence for the Lightly Doped Drain, LDD, engineering of the FET device. After defining the polysilicon gate, the lateral width of the first set of spacers is subsequently reduced by using the slightly protruding periphery of the polysilicon gate as an anisotropic etch mask. The reduced width of the first set of spacers facilitates the ability of an LDD ion implant to slightly extend under the gate. A second set of spacers are then conventionally formed on the side walls of the first set of spacers, prior to source-drain ion implantation.
The above prior art was mainly focused on ways to reduce FET device switching times, by means of obtaining shorter channel lengths than would, otherwise, not be possible from a given generation of photolithography equipment. However, as previously discussed. there are other factors, such as parasitic device capacitance, that can impact device switching times. One relevant component of parasitic device capacitance that has already been a-dressed in the prior art. is gate to drain overlap capacitance, C.sub.gdo, which is also referred to as Miller Capacitance, C.sub.n. C.sub.gdo can be particularly significant, since its value can be effectively doubled for the frequent case of an FET device being operated in an inverter circuit. FIG. 1 shows a CMOS inverter circuit, along with a C.sub.gdo parasitic capacitor. The input gate voltage waveform is shown as a rapidly rising ramp from zero volts to +V.sub.dd. The output voltage waveform is shown as a corresponding rapidly falling ramp from +V.sub.dd to zero volts. Accordingly, from Gauss's Law, the initial stored charge on C.sub.gdo is equal to +C.sub.gdo V.sub.dd and the final stored charge on C.sub.gdo is equal to -C.sub.gdo V.sub.dd. Therefore the effective electrical gate input capacitance to the inverter circuit can be calculated from dividing the change in charge on C.sub.gdo, 2C.sub.gdo V.sub.dd, by the change in the input voltage, V.sub.dd, which yields a value of 2C.sub.gdo. Therefore, the effective C.sub.gdo component of loading capacitance, looking into the inverter stage will actually be doubled. The above electrical effects of G.sub.dgo, also referred to Miller Capacitance, are well known and are described in J. Y. Chen, CMOS Devices and Technology for VLSI, pp. 100-101 (Prentice Hall 1990), which is incorporated herein by reference.
Gate to drain overlap capacitance, C.sub.gdo, along with the above electrical doubling effect of C.sub.gdo, can have a significant impact on device switching speed. Accordingly, this has prompted a series of innovations for minimizing the relative impact of C.sub.gdo, on switching times, as FET device technology has continued to evolve. Such innovations include the tailoring of source-drain ion implant angles and gate spacers, in order to obtain sufficient gate overlap of source-drains for maintaining low channel resistance, while still minimizing the associated C.sub.gdo values. In addition, efforts have also been made to minimize C.sub.gdo, by means of a Graded Gate Oxide, GGO, process, which locally increases the gate oxide thickness in the region of gate to drain overlap. Graded Gate Oxide, GGO, processing has been accomplished, for example, by using a wet ambient at about 850 C, in order to increase a 70 A.degree. gate oxide to about 250 A.degree., at the edge of the gate. The above process improvements for reducing gate to drain overlap capacitance are described in S. Wolf, Silicon Processing for the VLSI Era, Vol. 3, pp. 630-635 (Lattice Press 1995), which is incorporated herein by reference.
While various implementations of the above Graded Gate Oxide, GGO, process can help to reduce gate to drain overlap capacitance, GGO does have its own set of problems. For example, interface states generated by the reoxidation step can lead in increased hot electron related instability. Further more, the GGO process has been found to be difficult to control, particularly for deep sub micron devices. Consequently, there is a need for an alternative to the method for Graded Gate Oxide, GGO, processing, that is more compatible with device and manufacturing needs associated with the fabrication of state of the art deep sub micron devices. The present invention solves this need by providing a graded gate oxide layer that is largely graded in terms of its dielectric constant, as opposed to its thickness. Accordingly, an innovative method for forming localized regions of low dielectric constant, K, oxide in gate to drain overlap regions will now be described.